Integrated semiconductor memory circuits, particularly those employing cells which include essentially a storage capacitor and a switch have achieved relatively high memory cell densities. One of the simplest circuits for providing small memory cells is described in commonly assigned U.S. Pat. No. 3,387,286 filed July 14, 1967, by R. H. Dennard. Each of these cells employs a storage capacitor and a field effect transistor acting as a switch to selectively connect the capacitor to a bit/sense line. In also commonly assigned U.S. Pat. No. 3,811,076 by W. M. Smith and U.S. Pat. No. 3,841,926 by R. H. Garnache and W. M. Smith, both filed Jan. 2, 1973, t here is disclosed a one device field effect transistor memory cell of the type described in the above identified Dennard patent which utilizes a layer of doped polysilicon and an N+ diffusion region in a P type semiconductor substrate separated by a dielectric medium disposed on the surface of the semiconductor substrate for forming the storage capacitor of the cell. The polysilicon layer extends beyond the storage capacitor to act as a field shield between adjacent cells by applying a negative bias or fixed negative potential to the polysilicon layer.
As is known, these memory arrays require peripheral circuits, such as, decoders and sense amplifiers, for writing data into and reading data out of the memory arrays. Isolation regions between devices of the peripheral circuits often have different electrical requirements, e.g., different threshold voltages, compared to the requirements of the isolation regions located between the cells of the memory array. Since in many arrays, such as, those fabricated by known polysilicon processes using a polysilicon storage capacitor plate biased at one half or less of the voltage of the voltage supply source, the threshold voltage requirement on the isolation region separating the cells, particularly between cell storage nodes, may be relaxed compared to that of the isolation separating the peripheral devices. Consequently, a thinner isolating insulation layer may be used between the cell nodes of the array than that required between the devices or transistors of the peripheral circuits. A thinner isolating insulation layer or region has the advantages of reducing the well known "bird's beak" and, thus, increasing the storage capacitor area of the cell storage nodes, and decreasing the incidence of stress and topography related defects to provide improved yield.
In IBM Technical Disclosure Bulletin, Vol. 27, No. 11, April 1985, pp. 6422-6424, an article "Dual ROX Dynamic RAM Array" by D. L. Critchlow, W. P. Noble and W. W. Walker, discloses a process for making recessed oxide isolation layers having two different thicknesses which require the use of two critically aligned masks, as do the processes described in U.S. Pat. No. 4,326, 329, filed Feb. 28, 1980, and in IEDM 82, pp. 616-619, in an article entitled "A High Density, High Performance 1 T DRAM Cell", by A. Mohsen et al.
Commonly assigned U.S. Pat. No. 4,462,151, filed on Dec. 3, 1982, by H. J. Geipel, R. R. Troutman and J. M. Wursthorn, discloses a semiconductor process wherein openings are formed in a layer of silicon nitride with a single mask to define a plurality of spaced apart elements along the surface of the substrate and then one of the openings is protected by a later of material. However, there is no teaching to form within these openings insulating layers having different thicknesses.
U.S. Pat. Nos. 4,471,373, filed on Jan. 7, 1981, and 4,525,811, filed on Jan. 29, 1982, teach growing a first gate oxide layer and subsequently growing a second gate oxide layer of different thickness than the first oxide layer for field effect transistors.